Btsc encoder

ABSTRACT

The disclosed BTSC encoder includes a left high pass filter means; a matrix means for receiving the digital left and digital right filtered signals, and including means for summing the digital left and digital right filtered signals and thereby generating a digital sum signal, and including means for subtracting one of the digital left and digital right filtered signals from the other of the digital left and digital right filtered signals and thereby generating a digital difference signal; a difference channel processing means for digitally processing the digital difference signal; and a sum channel processing means for digitally processing the digital sum signal.

This patent application is a continuation of U.S. Application Ser. No.13/011,396, filed Jan. 21, 2011; which is a continuation of U.S.application Ser. No. 09/638,245, filed Aug. 14, 2000; which is acontinuation of U.S. application Ser. No. 09/041,244, filed Mar. 12,1998, now U.S. Pat. No. 6,118,879, issued Sep. 12, 2000; which is adivisional of U.S. application Ser. No. 08/661,412, filed Jun. 7, 1996,now U.S. Pat. No. 5,796,842, issued Aug. 18, 1998. The contents of eachof the earlier applications are hereby incorporated by reference asrecited herein in their entirety.

FIELD OF THE INVENTION

The present invention relates generally to stereophonic audio encodersused for television broadcasting. More particularly, the inventionrelates to a digital encoder for generating the audio signals used inthe broadcast of stereophonic television signals in the United Statesand in other countries.

BACKGROUND OF THE INVENTION

In the 1980's, the United States Federal Communications Commission (FCC)adopted new regulations covering the audio portion of television signalswhich permitted television programs to be broadcast and received withbichannel audio, e.g., stereophonic sound. In those regulations, the FCCrecognized and gave special protection to a method of broadcastingadditional audio channels endorsed by the Electronic IndustriesAssociation and the National Association of Broadcasters and called theBroadcast Television Systems Committee (BTSC) system. This well knownstandard is sometimes referred to as Multichannel Television Sound (MTS)and is described in the FCC document entitled, MULTICHANNEL TELEVISIONSOUND TRANSMISSION AND AUDIO PROCESSING REQUIREMENTS FOR THE BTSC SYSTEM(OET Bulletin No. 60, Revision A, February 1986), as well as in thedocument published by the Electronic Industries Association entitled,MULTICHANNEL TELEVISION SOUND BTSC SYSTEM RECOMMENDED PRACTICES (EIATelevision Systems Bulletin No. 5, July 1985). Television signalsgenerated according to the BTSC standard are referred to hereinafter as“BTSC signals”.

The original monophonic television signals carried only a single channelof audio. Due to the configuration of the monophonic television signaland the need to maintain compatibility with existing television sets,the stereophonic information was necessarily located in a higherfrequency region of the BTSC signal making the stereophonic channel muchnoisier than the monophonic audio channel. This resulted in aninherently higher noise floor for the stereo signal than for themonophonic signal. The BTSC standard overcame this problem by definingan encoding system that provided additional signal processing for thestereophonic audio signal. Prior to broadcast of a BTSC signal by atelevision station, the audio portion of a television program is encodedin the manner prescribed by the BTSC standard, and upon reception of aBTSC signal a receiver (e.g., a television set) then decodes the audioportion in a complementary manner. This complementary encoding anddecoding insures that the signal-to-noise ratio of the entire stereoaudio signal is maintained at acceptable levels.

FIG. 1 is a block diagram of a prior art BTSC encoding system, or moresimply, a BTSC encoder 100, as defined by the BTSC standard. Encoder 100receives left and right channel audio input signals (indicated in FIG. 1as “L” and “R”, respectively) and generates therefrom a conditioned sumsignal and an encoded difference signal. It should be appreciated thatwhile the system of the prior art and that of the present invention isdescribed as useful for encoding the left and right audio signals of astereophonic signal that is subsequently transmitted as a televisionsignal, the BTSC system also provides means to encode a separate audiosignal, e.g., audio information in a different language, which isseparated and selected by the end receiver. Further, noise reductioncomponents of the BTSC encoding system can be used for other purposesbesides television broadcast, such as for improving audio recordings.

System 100 includes an input section 110, a sum channel processingsection 120, and a difference channel processing section 130. Inputsection 110 receives the left and right channel audio input signals andgenerates therefrom a sum signal (indicated in FIG. 1 as “L+R”) and adifference signal (indicated in FIG. 1 as “L−R”). It is well known thatfor stereophonic signals, the sum signal L+R may be used by itself toprovide monophonic audio reproduction and it is this signal that isdecoded by existing monophonic audio television sets to reproduce sound.In stereophonic sets, the sum and difference signals can be added to andsubtracted from one another to recover the original two stereophonicsignals (L) and (R). Input section 110 includes two signal adders 112,114. Adder 112 sums the left and right channel audio input signals togenerate the sum signal, and adder 114 subtracts the right channel audioinput signal from the left channel audio input signal to generate thedifference signal. As described above, the sum signal L+R is transmittedthrough a transmission media with the same signal to noise ratio asachieved with the prior monophonic signals. However, the differencesignal L−R is transmitted though a very noisy channel, particularly atthe higher frequency portion of the relevant spectrum so that thedecoded difference signal has a poorer signal-to-noise ratio because ofthe noisy medium and reduced dynamic range of the medium. The dynamicrange is defined as the range of signals between the level of the noisefloor and the maximum level where signal saturation occurs. In thedifference signal channel the dynamic range decreases at higherfrequencies. Accordingly, the difference signal is subjected toadditional processing than that of the sum signal so that the dynamicrange can be substantially preserved.

More particularly, the sum channel processing section 120 receives thesum signal and generates therefrom the conditioned sum signal. Section120 includes a 75 μs preemphasis filter 122 and a bandlimiter 124. Thesum signal is applied to the input of filter 122 which generatestherefrom an output signal that is applied to the input of bandlimiter124. The output signal generated by the latter is then the conditionedsum signal.

The difference channel processing section 130 receives the differencesignal and generates therefrom the encoded difference signal. Section130 includes a fixed preemphasis filter 132 (shown implemented as acascade of two filters 132 a and 132 b), a variable gain amplifier 134preferably in the form of a voltage-controlled amplifier, a variablepreemphasis/deemphasis filter (referred to hereinafter as a “variableemphasis filter”) 136, an overmodulation protector and bandlimiter 138,a fixed gain amplifier 140, a bandpass filter 142, an RMS level detector144, a fixed gain amplifier 146, a bandpass filter 148, an RMS leveldetector 150, and a reciprocal generator 152.

The difference signal is applied to the input of fixed preemphasisfilter 132 which generates therefrom an output signal that is appliedvia line 132 d to an input terminal of amplifier 134. An output signalgenerated by reciprocal generator 152 is applied via line 152 a to again control terminal of amplifier 134. Amplifier 134 generates anoutput signal by amplifying the signal on line 132 d using a gain thatis proportional to the value of the signal on line 152 a. The outputsignal generated by amplifier 134 is applied via line 134 a to an inputterminal of variable emphasis filter 136, and an output signal generatedby RMS detector 144 is applied via line 144 a to a control terminal offilter 136. Variable emphasis filter 136 generates an output signal bypreemphasizing or deemphasizing the high frequency portions of thesignal on line 134 a under the control of the signal on line 144 a. Theoutput signal generated by filter 136 is applied to the input ofovermodulation protector and bandlimiter 138 which generates therefromthe encoded difference signal.

The encoded difference signal is applied via feedback path 138 a to theinputs of fixed gain amplifiers 140, 146, which amplify the encodeddifference signal by Gain A and Gain B, respectively. The amplifiedsignal generated by amplifier 140 is applied to an input of bandpassfilter 142 which generates therefrom an output signal that is applied tothe input of RMS level detector 144. The latter generates an outputsignal as a function of the RMS value of the input signal level receivedfrom filter 142. The amplified signal generated by amplifier 146 isapplied to the input of bandpass filter 148 which generates therefrom anoutput signal that is applied to the input of RMS level detector 150.The latter generates an output signal as a function of the RMS value ofthe input signal level received from filter 148. The output signal ofdetector 150 is applied via line 150 a to reciprocal generator 152,which generates a signal on line 152 a that is representative of thereciprocal of the value of the signal on line 150 a. As stated above,the output signals generated by RMS level detector 144 and reciprocalgenerator 152 are applied to filter 136 and amplifier 134, respectively.

As shown in FIG. 1, the difference channel processing section 130 isconsiderably more complex than the sum channel processing section 120.The additional processing provided by the difference channel processingsection 130, in combination with complementary processing provided by adecoder (not shown) receiving a BTSC signal, maintains thesignal-to-noise ratio of the difference channel at acceptable levelseven in the presence of the higher noise floor associated with thetransmission and reception of the difference channel. Difference channelprocessing section 130 essentially generates the encoded differencesignal by dm compressing, or reducing the dynamic range of thedifference signal so that the encoded signal may be transmitted throughthe limited dynamic range transmission path associated with a BTSCsignal, and so that a decoder receiving the encoded signal may recoverall the dynamic range in the original difference signal by expanding thecompressed difference signal in a complementary fashion. The differencechannel processing section 130 is a particular form of the adaptivesignal weighing system described in U.S. Pat. No. 4,539,526, which isknown to be advantageous for transmitting a signal having a relativelylarge dynamic range through a transmission path having a relativelynarrow, frequency dependent, dynamic range.

Briefly, the difference channel processing section may be thought of asincluding a wide band compression unit 180 and a spectral compressionunit 190. The wide band compression unit 180 includes variable gainamplifier 134 preferably in the form of a voltage controlled amplifier,and the components of the feedback path for generating the controlsignal to amplifier 134 and comprising amplifier 146, band pass filter148, RMS level detector 150, and reciprocal generator 152. Band passfilter 148 has a relatively wide pass band, weighted towards lower audiofrequencies, so in operation the output signal generated by filter 148and applied to RMS level detector 150 is substantially representative ofthe encoded difference signal. RMS level detector 150 thereforegenerates an output signal on line 150 a representative of a weightedaverage of the energy level of the encoded difference signal, andreciprocal generator 152 generates a signal on line 152 a representativeof the reciprocal of this weighted average. The signal on line 152 acontrols the gain of amplifier 134, and since this gain is inverselyproportional to a weighted average (i.e., weighted towards lower audiofrequencies) of the energy level of the encoded difference signal, wideband compression unit 180 “compresses”, or reduces the dynamic range, ofthe signal on line 132 a by amplifying signals having relatively lowamplitudes and attenuating signals having relatively large amplitudes.

The spectral compression unit 190 includes variable emphasis filter 136and the components of the feedback path generating a control signal tothe filter 136 and comprising amplifier 140, band pass filter 142 andRMS level detector 144. Unlike filter 148, band pass filter 142 has arelatively narrow pass band that is weighted towards higher audiofrequencies. As is well known, the transmission medium associated withthe difference portion of the BTSC transmission system has a frequencydependent dynamic range and the pass band of filter 142 is chosen tocorrespond to the spectral portion of that transmission path having thenarrowest dynamic range (i.e., the higher frequency portion). Inoperation the output signal generated by filter 142 and applied to RMSlevel detector 144 contains primarily the high frequency portions of theencoded difference signal. RMS level detector 144 therefore generates anoutput signal on line 144 a representative of the energy level in thehigh frequency portions of the encoded difference signal. This signalthen controls the preemphasis/deemphasis applied by variable emphasisfilter 136 so in effect the spectral compression unit 190 dynamicallycompresses high frequency portions of the signal on line 134 a by anamount determined by the energy level in the high frequency portions ofthe encoded difference signal as determined by the filter 142. The useof the spectral compression unit 190 thus provides additional signalcompression towards the higher frequency portions of the differencesignal, which combines with the wideband compression provided by thevariable gain amplifier 134 to effectively cause more overallcompression to take place at high frequencies relative to thecompression at lower frequencies. This is done because the differencesignal tends to be noisier in the higher frequency part of the spectrum.When the encoded difference signal is decoded with a wideband expanderand a spectral expander in a decoder (not shown), respectively in acomplementary manner to the wide band compression unit 180 and spectralcompression unit 190 of the encoder, the signal-to-noise ratio of theL−R signal applied to the difference channel processing section 130 willbe substantially preserved.

The BTSC standard rigorously defines the desired operation of the 75 μspreemphasis filter 122, the fixed preemphasis filter 132, the variableemphasis filter 136, and the bandpass filters 142, 148, in terms ofidealized analog filters. Specifically, the BTSC standard provides atransfer function for each of these components and the transferfunctions are described in terms of mathematical representations ofidealized analog filters. The BTSC standard also defines the gainsettings, Gain A and Gain B, of amplifiers 140 and 146, respectively,and also defines the operation of amplifier 134, RMS level detectors144, 150, and reciprocal generator 152. The BTSC standard also providessuggested guidelines for the operation of overmodulation protector andbandlimiter 138 and bandlimiter 124. Specifically, bandlimiter 124 andthe bandlimiter portion of overmodulation protector and bandlimiter 138are described as low pass filters with cutoff frequencies of 15 kHz, andthe overmodulation protection portion of overmodulation protector andbandlimiter 138 is described as a threshold device that limits theamplitude of the encoded difference signal to 100% of full modulationwhere full modulation is the maximum permissible deviation level formodulating the audio subcarrier in a television signal.

Since encoder 100 is defined in terms of mathematical descriptions ofidealized filters it may be thought of as an idealized or theoreticalencoder, and those skilled in the art will appreciate that it isvirtually impossible to construct a physical realization of a BTSCencoder that exactly matches the performance of theoretical encoder 100.Therefore, it is expected that the performance of all BTSC encoders willdeviate somewhat from the theoretical ideal, and the BTSC standarddefines maximum limits on the acceptable amounts of deviation. Forexample, the BTSC standard states that a BTSC encoder must provide atleast 30 db of separation from 100 Hz to 8,000 Hz where separation is ameasure of how much a signal applied to only one of the left or rightchannel's inputs appears erroneously in the other of the left or rightchannel's outputs.

The BTSC standard also defines a composite stereophonic baseband signal(referred to hereinafter as the “composite signal”) that is used togenerate the audio portion of a BTSC signal. The composite signal isgenerated using the conditioned sum signal, the encoded differencesignal, and a tone signal, commonly referred to as the “pilot tone” orsimply as the “pilot”, which is a sine wave at a frequency f_(H) wheref_(H) is equal to 15,734 Hz. The presence of the pilot in a receivedtelevision signal indicates to the receiver that the television signalis a BTSC signal rather than a monophonic or other non BTSC signal. Thecomposite signal is generated by multiplying the encoded differencesignal by a waveform that oscillates at twice the pilot frequencyaccording to the cosine function cos(4πf_(H)t), where t is time, togenerate an amplitude modulated, double-sideband, suppressed carriersignal and by then adding to this signal the conditioned sum signal andthe pilot tone.

FIG. 2 is a graph of the spectrum of the composite signal. In FIG. 2 thespectral band of interest containing the content of the conditioned sumsignal (or the “sum channel signal”) is indicated as “L+R”, the twospectral sidebands containing the content of the frequency shiftedencoded difference signal (or the “difference channel signal”) are eachindicated as “L−R”, and the pilot tone is indicated by the arrow atfrequency f_(H). As shown in FIG. 2, in the composite signal the encodeddifference signal is used at 100% of full modulation, the conditionedsum signal is used at 50% of full modulation, and the pilot tone is usedat 10% of full modulation.

Stereophonic television has been widely successful, and existingencoders have performed admirably, however, virtually every BTSC encodernow in use has been built using analog circuitry technology. Theseanalog BTSC encoders, and particularly the analog difference channelprocessing sections, due to their increased complexity have beenrelatively difficult and expensive to construct. Due to the variabilityof analog components, complex component selection and extensivecalibration have been required to produce acceptable analog differencechannel processing sections. Further, the tendency of analog componentsto drift, over time, away from their calibrated operating points hasalso made it difficult to produce an analog difference channelprocessing section that consistently and repeatably performs within agiven tolerance. A digital difference channel processing section, if onecould be built, would not suffer from these problems of componentselection, calibration, and performance drift, and could potentiallyprovide increased performance.

Further, the analog nature of existing BTSC encoders has made theminconvenient to use with newly developed, increasingly popular, digitalequipment. For example, television programs can now be stored usingdigital storage media such as a hard disk or digital tape, rather thanthe traditional analog storage media, and in the future increasing usewill be made of digital storage media. Generating a BTSC signal from adigitally stored program now requires converting the digital audiosignals to analog signals and then applying the analog signals to ananalog BTSC encoder. A digital BTSC encoder, if one could be built,could accept the digital audio signals directly and could therefore bemore easily integrated with other digital equipment.

While a digital BTSC encoder would potentially offer several advantages,there is no simple way to construct an encoder using digital technologythat is functionally equivalent to the idealized encoder 100 defined bythe BTSC standard. One problem is that the BTSC standard defines all thecritical components of idealized encoder 100 in terms of analog filtertransfer functions. As is well known, while it is generally possible todesign a digital filter so that either the magnitude or the phaseresponse of the digital filter matches that of an analog filter, it isextremely difficult to match both the amplitude and phase responseswithout requiring large amounts of processing capacity for processingdata sampled at very high sampling rates or without significantlyincreasing the complexity of the digital filter. Without increasingeither the sampling frequency or the filter order, the amplituderesponse of a digital filter can normally only be made to more closelymatch that of an analog filter at the expense of increasing thedisparity between the phase responses of the two filters, and viceversa. However, since small errors in either amplitude or phase decreasethe amount of separation provided by BTSC encoders, it would beessential for a digital BTSC encoder to closely match both the amplitudeand phase responses of an idealized encoder of the type shown at 100 inFIG. 1.

For a digital BTSC encoder to provide acceptable performance, it iscritical to preserve the characteristics of the analog filters of anidealized encoder 100. Various techniques exist for designing a digitalfilter to match the performance of an analog filter; however, ingeneral, none of these techniques produce a digital filter (of the sameorder as the analog filter) having amplitude and phase responses thatexactly match the corresponding responses of the analog filter. Idealencoder 100 is defined in terms of analog transfer functions specifiedin the frequency domain, or the s-plane, and to design a digital BTSCencoder, these transfer functions must be transformed to the z-plane.Such a transformation may be performed as a “many-to-one” mapping fromthe s-plane to the z-plane which attempts to preserve time domaincharacteristics. However, in such a transformation the frequency domainresponses are subject to aliasing and may be altered significantly.Alternatively, the transformation may be performed as a “one-to-one”mapping from the s-plane to the z-plane that compresses the entires-plane into the unit circle of the z-plane. However, such a compressionsuffers from the familiar “frequency warping” between the analog anddigital frequencies. Prewarping can be employed to compensate for thisfrequency warping effect, however, prewarping does not completelyeliminate the deviations from the desired frequency response. Theseproblems would have to be overcome to produce a digital BTSC encoderthat performs well and is not unduly complex or expensive.

There is therefore a need for overcoming the difficulties and developinga digital BTSC encoder.

OBJECTS OF THE INVENTION

It is an object of the present invention to substantially reduce orovercome the above-identified problems of the prior art.

Another object of the present invention is to provide an adaptivedigital weighing system.

Still another object of the present invention is to provide an adaptivedigital weighing system for encoding an electrical information signal ofa predetermined bandwidth so that the information signal can be recordedon or transmitted through a dynamically-limited, frequency dependentchannel having a narrower dynamically-limited portion in a fast spectralregion than in at least one other spectral region of the predeterminedbandwidth.

And another object of the present invention is to provide a digital BTSCencoder.

Yet another object of the present invention is to provide a digital BTSCencoder that prevents ticking, a problem that can arise withsubstantially zero input signal levels.

And another object of the present invention is to provide a digital BTSCencoder that uses a sampling frequency that is a multiple of a pilottone signal frequency of 15,734 Hz so as to prevent interference betweenthe signal information of the encoded signal with the pilot tone signal.

Still another object of the invention is to provide a digital BTSCencoder for generating a conditioned sum signal and an encodeddifference signal that include substantially no signal energy at thepilot tone frequency of 15,734 Hz.

Yet another object of the present invention is to provide a digital BTSCencoder including a sum channel processing section for generating theconditioned sum signal, and a difference processing section forgenerating the encoded difference signal, the sum channel processingsection including devices for introducing compensatory phase errors intothe conditioned sum signal to compensate for any phase errors introducedinto the encoded difference signal by the difference channel processingsection.

And another object of the present invention is to provide a digital BTSCencoder including a digital variable emphasis unit, the unit including adigital variable emphasis filter characterized by a variable coefficienttransfer function, and the unit further including a device for selectingthe coefficients of the variable coefficient transfer function as afunction of the signal energy of the encoded difference signal.

Yet another object of the present invention is to provide a digital BTSCencoder including a composite modulator for generating a compositemodulated signal from the conditioned sum signal and the encodeddifference signal.

Still another object of the present invention is to provide a digitalBTSC encoder that may be implemented on a single integrated circuit.

SUMMARY OF THE INVENTION

These and other objects are provided by an improved BTSC encoder thatincludes an input section, a sum channel processing section, and adifference channel processing section all of which are implemented usingdigital technology. In one aspect, the input section includes high passfilters for preventing the BTSC encoder from exhibiting “ticking”. Inanother aspect, the BTSC encoder uses a sampling frequency that is equalto an integer multiple of the pilot frequency.

In yet another aspect, the sum channel processing section generates aconditioned sum signal, and the difference channel processing sectiongenerates an encoded difference signal, and the sum channel processingsection includes components for introducing a phase error into theconditioned sum signal to compensate for any phase errors introducedinto the encoded difference signal by the difference channel processingsection.

According to yet another aspect, the invention provides an adaptivedigital weighing system for encoding an electrical information signal ofa predetermined bandwidth so that the information signal can be recordedon or transmitted through a dynamically-limited, frequency dependentchannel having a narrower dynamically-limited portion in a fast spectralregion than in at least one other spectral region of the predeterminedbandwidth.

Still other objects and advantages of the present invention will becomereadily apparent to those skilled in the art from the following detaileddescription wherein several embodiments are shown and described, simplyby way of illustration of the best mode of the invention. As will berealized, the invention is capable of other and different embodiments,and its several details are capable of modifications in variousrespects, all without departing from the invention. Accordingly, thedrawings and description are to be regarded as illustrative in nature,and not in a restrictive or limiting sense, with the scope of theapplication being indicated in the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

For a fuller understanding of the nature and objects of the presentinvention, reference should be had to the following detailed descriptiontaken in connection with the accompanying drawings in which the samereference numerals are used to indicate the same or similar partswherein:

FIG. 1 shows a block diagram of a prior art idealized BTSC encoder;

FIG. 2 shows a graph of the spectrum of the composite signal generatedin accordance with the BTSC standards;

FIG. 3 shows a block diagram of one embodiment of a digital BTSC encoderconstructed according to the invention;

FIGS. 4A-C show block diagrams of low pass filters used in the digitalBTSC encoder shown in FIG. 3;

FIG. 5 shows a detailed block diagram of the wideband compression unitused in the digital BTSC encoder shown in FIG. 3;

FIG. 6 shows a block diagram of the spectral compression unit used inthe digital BTSC encoder shown in FIG. 3;

FIG. 7 shows a flow chart used for calculating the filter coefficientsof the variable emphasis filter used in the spectral compression unitshown in FIG. 6;

FIGS. 8A-D show block diagrams that illustrate signal scaling that maybe used to preserve resolution and decrease the chance of saturation infixed point implementations of digital BTSC encoders constructedaccording to the invention;

FIG. 9 shows a detailed block diagram of the composite modulator shownin FIGS. 8B-C; and

FIG. 10 shows a block diagram of one preferred embodiment of sum anddifference channel processing sections that may be used in digital BTSCencoders constructed according to the invention.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 3 is a block diagram of one embodiment of a digital BTSC encoder200 constructed according to the invention. Digital encoder 200 isconstructed to provide performance that is functionally equivalent tothe performance of idealized encoder 100 (shown in FIG. 1). As withidealized encoder 100, digital encoder 200 receives the left and rightchannel audio input signals and generates therefrom the conditioned sumsignal and the encoded difference signal, however, in digital encoder200 these input and output signals are digitally sampled signals ratherthan continuous analog signals.

The choice of sampling frequency f_(s) for the left and right channelaudio input signals significantly affects the design of digital encoder200. In the preferred embodiments, the sampling frequency f_(s) ischosen to be an integer multiple of the pilot frequency f_(H), so thatf_(s)=Nf_(n) where N is an integer, and in the most preferredembodiments, N is selected to be greater than or equal to three. It isimportant for encoder 200 to insure that the conditioned sum and encodeddifference signals do not contain enough energy at the pilot frequencyf_(H) to interfere with the pilot tone that is included in the compositesignal. As will be discussed in greater detail below, it is thereforedesirable for at least some of the filters in digital encoder 200 toprovide an exceptionally large degree of attenuation at’ the pilotfrequency f_(H), and this choice of sampling frequency f_(s) simplifiesthe design of such filters.

Digital encoder 200 includes an input section 210, a sum channelprocessing section 220 and a difference channel processing section 230.Rather than simply implementing the difference channel processingsection 230 using digital technology, all three sections 210, 220, 230are implemented entirely using digital technology. Many of theindividual components in digital encoder 200 respectively correspond toindividual components in idealized encoder 100. In general, thecomponents of digital encoder 200 have been selected so that theiramplitude responses closely match the respective amplitude responses oftheir corresponding components in encoder 100. This often results inthere being a relatively large difference between the phase responses ofcorresponding components. According to one aspect of the presentinvention, means are provided in digital encoder 200 for compensatingfor or nullifying these phase differences, or phase errors. As thoseskilled in the art will appreciate, relatively small phase errors in thedifference channel processing section 230 may be compensated for byintroducing similar phase errors in the sum channel processing section220, and implementing the sum channel processing section using digitaltechnology simplifies the introduction of such desired compensatingphase errors.

The input section 210 of encoder 200 includes two high pass filters 212,214, and two signal adders 216, 218. The left channel digital audioinput signal L is applied to the input of high pass filter 212, thelatter generating therefrom an output signal that is applied to positiveinput terminals of adders 216, 218. The right channel audio input signalR is applied to the input of high pass filter 214 which generatestherefrom an output signal that is applied to a positive input terminalof adder 216 and to a negative input terminal of adder 218. Adder 216generates a sum signal (indicated in FIG. 3 as “L+R”) by summing theoutput signals generated by filters 212 and 214. Adder 218 generates adifference signal (indicated in FIG. 3 as “L−R”) by subtracting theoutput signal generated by filter 214 from the output signal generatedby filter 212. Input section 210 is therefore similar to input section110 (shown in FIG. 1) however, section 210 additionally includes the twohigh pass filters 212, 214 and generates digital sum and differencesignals.

High pass filters 212, 214 preferably have substantially identicalresponses and preferably remove D.C. components from the left and rightchannel audio input signals. As will be discussed in greater detailbelow, this D.C. removal prevents encoder 200 from exhibiting a behaviorreferred to as “ticking”. Since the audio-information content of theleft and right channel audio input signals of interest is considered tobe within a frequency band between 50 Hz and 15,000 Hz, removal of D.C.components does not interfere with the transmission of the informationcontent of the audio signals. Filters 212, 214, therefore, preferablyhave a cutoff frequency below 50 Hz, and more preferably have a cutofffrequency below 10 Hz so that they will not remove any audio informationcontained in the audio input signals. Filters 212, 214 also preferablyhave a flat magnitude response in their passband. In one preferredembodiment, filters 212, 214 are implemented as first order infiniteimpulse response (IIR) filters, each having a transfer function H(z)given by the formula shown in the following Equation (1).

$\begin{matrix}{{H(z)} = \frac{1 - z^{- 1}}{1 + {a_{1}z^{- 1}}}} & (1)\end{matrix}$

Referring again to FIG. 3, the sum channel processing section 220receives the sum signal and generates therefrom the conditioned sumsignal. In particular, the sum signal is applied to a 75 μs preemphasisfilter 222. The filter 222 in turn generates an output signal that isapplied to a static phase equalization filter 228. The filter 228generates an output signal that is applied to a low pass filter 224 ofsection 220 which in turn generates the conditioned sum signal.

The 75 μs preemphasis filter 222 provides signal processing that ispartially analogous to the filter 122 (shown in FIG. 1) of idealizedencoder 100. The amplitude response of filter 222 is preferably selectedto closely match that of filter 122. As will be discussed further below,means are preferably provided in difference channel processing section230 for compensation for any differences in the phase responses offilters 222 and 122. In one preferred embodiment, filter 222 isimplemented as a fast order IIR filter having a transfer function H(z)that is described by the formula shown in the following Equation (2).

$\begin{matrix}{{H(z)} = \frac{b_{0} + {b_{1}z^{- 1}}}{1 + {a_{1}z^{- 1}}}} & (2)\end{matrix}$

Static phase equalization filter 228 performs processing that is notdirectly analogous to any of the components in idealized encoder 100(shown in FIG. 1). As will be discussed in greater detail below, staticphase equalization filter 228 is used to introduce phase errors thatcompensate for phase errors introduced by difference processing section230. Briefly, static phase equalization filter 228 is preferably an“all-pass” filter having a relatively flat amplitude response and aselected phase response. In one preferred embodiment, filter 228 isimplemented as a first order IIR filter having a transfer function H(z)that is described by the formula shown in the following Equation (3).

$\begin{matrix}{{H(z)} = \frac{a_{0} + z^{- 1}}{1 + {a_{0}z^{- 1}}}} & (3)\end{matrix}$

Low pass filter 224 provides processing that is partially analogous tobandlimiter 124 (shown in FIG. 1) of encoder 100. Low pass filter 224preferably provides a flat amplitude response in a pass band of zero to15 kHz and a relatively sharp cutoff above 15. Filter 224 alsopreferably provides an exceptionally large degree of attenuation at thefrequency f_(H) of the pilot tone (i.e., 15,734 Hz). By providing thisexceptionally large degree of attenuation, filter 224 insures that theconditioned sum signal does not include enough energy at the pilotfrequency f_(H) to interfere with the pilot tone used in the compositesignal. As discussed above, selecting the sampling frequency f_(s) to beequal to an integer multiple of the pilot frequency f_(H) simplifies thedesign of a filter that provides an exceptionally large degree ofattenuation at the pilot frequency and therefore simplifies the designof filter 224. Filter 224 preferably has a null at the pilot frequencyf_(H) and preferably provides at least 70 dB of attenuation for allfrequencies from the pilot frequency f_(H) up to one-half the samplerate.

FIG. 4A is a block diagram illustrating one preferred embodiment of lowpass filter 224. As shown in FIG. 4A, filter 224 may be implemented bycascading five filter sections 310, 312, 314, 316, 318. In one preferredembodiment, all five filter sections 310, 312, 314, 316, 318 are eachimplemented as a second order IIR filter having transfer functions H(z)which are described by the formula shown in the following Equation (4).

$\begin{matrix}{{H(z)} = \frac{b_{0} + {b_{1}z^{- 1}} + {bz}^{- 2}}{1 + {a_{1}z^{- 1}} + {a_{2}z^{- 2}}}} & (4)\end{matrix}$

So in the embodiment shown in FIG. 4A, filter 224 is tenth order IIRfilter.

Referring again to FIG. 3, the difference channel processing section 230receives the difference signal and generates therefrom the encodeddifference signal. The difference signal is applied to a low pass filter238 a which generates therefrom an output signal that is applied to afixed preemphasis filter 232 a. The latter generates an output signalthat is applied via line 239 to an input terminal of a widebandcompression unit 280, and the encoded difference signal is applied viafeedback line 240 to a detector terminal of wideband compression unit280. The latter generates an output signal that is applied via line 281to an input terminal of a spectral compression unit 290, and the encodeddifference signal is also applied via feedback line 240 to a detectorterminal of unit 290. The latter generates an output signal that isapplied to a fixed preemphasis filter 232 b which in turn generates anoutput signal that is applied to a clipper 254. Clipper 254 generates anoutput signal that is applied to a low pass filter 238 b which in turngenerates the encoded difference signal.

Low pass filters 238 a, 238 b, together form a low pass filter 238 thatperforms processing that is partially analogous to the bandlimiterportion of overmodulation protector and bandlimiter 138 (shown inFIG. 1) of idealized encoder 100. Preferably, filter 238 is implementedso that it is substantially identical to low pass filter 224, which isused in the sum channel processing section 220. Any phase errorsintroduced into the encoded difference signal by filter 238 aretherefore compensated by balancing phase errors that are introduced intothe conditioned sum signal by filter 224. Filter 238 is preferably splitinto two sections 238 a, 238 b as shown for reasons which will bediscussed in greater detail below, and filter 238 a preferably has anull at the pilot frequency f_(H).

FIGS. 4B-C are block diagrams illustrating one preferred embodiment ofthe respective filters 238 a and 238 b. As shown in FIG. 4B, filter 238a may be implemented by cascading three filter sections 310, 314, 318that are identical to three of the filter sections used in filter 224(shown in FIG. 4A), and as shown in FIG. 4C, filter 238 b may beimplemented by cascading two filter sections 312, 316 that are identicalto the two remaining sections used in filter 224.

Fixed preemphasis filters 232 a, 232 b (shown in FIG. 3) together form afixed preemphasis filter 232 that performs processing that is partiallyanalogous to filter 132 (shown in FIG. 1) of idealized encoder 100. Theamplitude response of filter 232 is preferably selected to closely matchthe amplitude response of filter 132. In one embodiment, the phaseresponses of filters 232 and 132 are significantly different, and aswill be discussed in greater detail below, the resulting phase errorsare compensated for by filters 222 and 228 in the sum channel processingsection 220. Filter 232 is preferably split into two sections 232 a, 232b as shown for reasons that will be discussed below. In one preferredembodiment, filters 232 a, 232 b are each implemented as first order IIRfilters having transfer functions H(z) that are described by the formulashown in Equation (2). So in this embodiment filter 232 is a secondorder IIR filter.

In one preferred embodiment, the difference between the phase responsesof filters 232 b and 132 a closely matches the difference between thephase responses of filters 222 and 122. Therefore, the phase errorintroduced into the encoded difference signal by fixed preemphasisfilter 232 b is balanced by the phase error introduced into theconditioned sum signal by 75 μs preemphasis filter 222. Further, in thisembodiment, the phase response of static phase equalization filter 228is selected to closely match the difference between the phase responsesof fixed preemphasis filter 232 a and filter 132 b, so that any phaseerror introduced into the encoded difference signal by filter 232 a isbalanced by a compensatory phase error in the conditioned sum signalthat is introduced by static phase equalization filter 228.

Clipper 254 performs processing that is partially analogous to theovermodulation protection portion of overmodulation protector andbandlimiter 138 (shown in FIG. 1) used in idealized encoder 100.Briefly, clipper 254 is implemented as a thresholding device, however,the operation of clipper 254 will be discussed in greater detail below.

Wideband compression unit 280 and spectral compression unit 290 performprocessing functions that are partially analogous to that of units 180and 190, respectively, of idealized encoder 100 (shown in FIG. 1).Briefly, wideband compression unit 280 dynamically compresses the signalon line 239 as a function of the overall energy level in the encodeddifference signal and spectral compression unit 290 further compresseshigh frequency portions of the signal on line 281 as a function of highfrequency energy in the encoded difference signal.

FIG. 5 shows a block diagram of a preferred embodiment of a digitalwideband compression unit 280. Unit 280 includes a digital signalmultiplier 434, a digital signal multiplier 446, a wideband digitalbandpass filter 448, a digital RMS level detector 450, and a digitalreciprocal generator 458. These components perform processing functionspartially analogous to those performed by amplifier 134, amplifier 146,bandpass filter 148, RMS level detector 150, and reciprocal generator152, respectively, of idealized encoder 100 (shown in FIG. 1). Theencoded difference signal is applied via feedback path 240 to an inputof wideband digital bandpass filter 448 which generates therefrom anoutput signal that is applied to RMS level detector 450. The lattergenerates an output signal that is representative of the RMS value ofthe output signal generated by filter 448 and applies this output signalvia line 450 a to reciprocal generator 458. Reciprocal generator 458then generates an output signal representative of the reciprocal of thesignal on line 450 a and applies this output signal via line 458 a tomultiplier 446. Digital signal multiplier 446 multiplies the signal online 458 a by the value of the gain setting, Gain D, and therebygenerates an output signal that is representative of D times thereciprocal of the RMS value and that is applied via line 446 a to aninput terminal of multiplier 434. The output signal generated by fixedpreemphasis filter 232 a is applied via line 239 to another inputterminal of multiplier 434. Multiplier 434 multiplies the signal on line239 by the signal on line 446 a and thereby generates the output ofwideband compression unit 280 which is applied via line 281 to the inputof spectral compression unit 290.

Wideband digital bandpass filter 448 is designed to have an amplituderesponse that closely matches the amplitude response of bandpass filter148 (shown in FIG. 1). One preferred choice is to select filter 448 sothat the mean square difference between its amplitude response and thatof filter 148 are minimised. In one embodiment, the phase response offilters 448 and 148 are substantially different, but since the outputsignal of the RMS level detector 450 is substantially insensitive to thephase of its input signal, these phase differences maybe ignored. In onepreferred embodiment, wideband bandpass filter 448 is implemented as asecond order IIR filter having a transfer function H(z) that isdescribed by the formula shown in Equation (4).

RMS level detector 450 is designed to approximate the performance ofdetector 150 which is used in idealized encoder 100 (shown in FIG. 1).Detector 450 includes a signal squaring device 452, a signal averagingdevice 454, and a square root device 456. Squaring device 452 squaresthe signal generated by bandpass filter 448 and applies this squaredsignal via line 452 a to averaging device 454. The latter computes atime weighted average of the signal on line 452 a and applies theaverage via line 454 a to square root device 456. Square root device 456calculates the square root of the signal on line 454 a and therebygenerates a signal on line 450 a representative of the RMS value of theoutput signal generated by wideband digital bandpass filter 448.

Averaging device 454 includes a digital signal multiplier 460, a digitalsignal adder 462, a digital signal multiplier 464, and a delay register465. The output signal generated by squaring device 452 is applied vialine 452 a to one input of multiplier 460 which generates an outputsignal by scaling the signal on line 452 a by a constant α. The scaledoutput signal generated by multiplier 460 is applied to one input ofadder 462 and an output signal generated by delay register 465 isapplied to the other input of adder 462. Adder 462 generates an outputsignal by summing the signals present at its two inputs, and this summedsignal is the output signal of averaging device 454 and is applied tosquare root device 456 via line 454 a. This summed signal is alsoapplied to one input of multiplier 464 which generates an output signalby scaling the summed signal by the constant (1−α). The output signalgenerated by multiplier 464 is applied to an input of delay register465. Those skilled in the art will appreciate that averager 454 is arecursive filter and implements a digital averaging function that isdescribed by the recursive formula shown in the following Equation (5).

y(n)=αx(n)+(1−α)y(n−1)  (5)

in which y(n) represents the current digital sample of the signal outputby averager 454 on line 454 a, y(n−1) represents the previous digitalsample of the signal output by averager 454 on line 454 a, and x(n)represents the current digital sample of the signal output by squaringdevice 452 on line 452 a. Those skilled in the art will appreciate thataverager 454 provides a digital approximation of the analog averagingfunction defined in the BTSC standard and implemented by RMS leveldetector 150 (shown in FIG. 1) of idealized encoder 100. The constant ais preferably chosen so that the time constant of RMS level detector 450closely approximates the corresponding time constant specified in theBTSC standard for RMS level detector 150.

Digital square root device 456 and digital reciprocal generator 458 areshown in FIG. 5 as two separate components, however, those skilled inthe art will appreciate that these two components may be implementedusing a single device that generates an output signal representative ofthe reciprocal of the square root of its input signal. Such a device maybe implemented for example as a memory look up table (LUT), oralternatively may be implemented using processing components thatcalculate a Taylor series polynomial approximation of the inverse squareroot function.

FIG. 6 shows a block diagram of a preferred embodiment of spectralcompression unit 290. Unit 290 includes a variablepreemphasis/deemphasis unit (hereinafter referred to as the “variableemphasis unit”) 536, a signal multiplier 540, a spectral band passfilter 542, and an RMS level detector 544, and these components provideprocessing which is partially analogous to that of variable emphasisfilter 136, amplifier 140, bandpass filter 142, and RMS level detector144, respectively, of idealized encoder 100 (shown in FIG. 1). Theencoded difference signal is applied via feedback line 240 to an inputof signal multiplier 540 which generates an output signal by multiplyingthe encoded difference signal by the fixed gain setting value of Gain C.The amplified output signal generated by signal multiplier 540 isapplied to spectral bandpass filter 542 which generates an output signalthat is applied to RMS level detector 544. The latter generates anoutput signal that is applied via line 544 a to a control terminal ofvariable emphasis unit 536, and the output signal generated by widebandcompressor unit 280 is applied via line 281 to an input terminal of unit536. The latter dynamically varies the frequency response applied to thesignal on line 281 according to a function of the signal on line 544 a,the latter signal being a function of the signal energy of the encodeddifference signal within the frequency band passed by spectral band passfilter 542. The output signal of unit 290, which is generated by unit536 and is applied to the input of fixed preemphasis filter 232 b, isthus dynamically compressed a greater amount in the high frequencyportions of the signal than in the remainder of the spectrum ofinterest.

Spectral bandpass filter 542 is designed to have an amplitude responsethat closely matches the amplitude response of bandpass filter 142(shown in FIG. 1) of idealized encoder 100. As with filter 448 (shown inFIG. 5), one preferred choice is to select filter 542 so that thedifference between its RMS amplitude response and that of filter 142 areminimized. In one embodiment, the phase response of filters 542 and 142are substantially different, but since the RMS output of RMS leveldetector 544 is substantially insensitive to the phase of the input tothe detector, these phase differences may be ignored. In one preferredembodiment, spectral bandpass filter 542 is implemented as a cascade ofthree second order IIR filter sections 542 a, 542 b, 542 c (as shown inFIG. 6) each having a transfer function H(z) that is described by theformula shown in Equation (4).

RMS level detector 544 is designed to approximate the performance ofdetector 144 which is used in idealized encoder 100 (shown in FIG. 1).Detector 544 includes a signal squaring device 552, a signal averagingdevice 554, and a square root device 556. Squaring device 552 squaresthe signal generated by spectral bandpass filter 542 and applies thissquared signal via line 552 a to averaging device 554. The latterfunctions similarly to averaging device 454 (shown in FIG. 5) which isused in the wideband compression unit 280, although device 554preferably uses a constant β different from the constant α. The behaviorof averaging device 554 is of course also described by Equation (5) whenβ is substituted for α. The constant β is preferably selected for device554 so that the time constant of RMS level detector 544 closelyapproximates the corresponding time constant specified by the BTSCstandard for RMS level detector 144 (shown in FIG. 1). Averaging device554 computes a time weighted average of the signal on line 552 a andapplies the average to square root device 556 via line 554 a. Squareroot device 556 calculates the square root of the signal on line 554 aand thereby generates a signal on line 544 a as a function of the RMSvalue of the output signal generated by spectral bandpass filter 542.

The signal on line 544 a is applied to the control terminal of variableemphasis unit 536. Variable emphasis unit 536 performs processing thatis partially analogous to filter 136 (shown in FIG. 1) of idealizedencoder 100. As defined by the BTSC standard, filter 136 has amplitudeand phase responses that vary as a function of the output signalgenerated by RMS level detector 144. One preferred way to implement unit536 so that it has similar variable responses is to use a digital filterhaving variable coefficients that determine its transfer function and toselect the value of the coefficients during any given sample period, orgroup of sample periods, based on the value of the signal on line 544 a.

FIG. 6 shows one embodiment of variable emphasis unit 536 which includesa logarithmic generator 558, a variable emphasis filter 560, and a lookup table LUT 562. The output signal generated by RMS level detector 544is applied via line 544 a to logarithmic generator 558. The lattergenerates a signal on line 558 a that is representative of the logarithmof the signal on line 544 a and applies this signal to LUT 562. LUT 562generates an output signal selected from the LUT and: representative offilter coefficients to be used by variable emphasis filter 560. Thecoefficients thus generated by LUT 562 are applied via line 562 a to acoefficient selection terminal of variable emphasis filter 560. Theoutput signal generated by wideband compression unit 280 is applied toan input terminal of variable emphasis filter 560 via line 281. Variableemphasis filter 560 generates the output signal of spectral compressionunit 290 which is applied to the input of fixed preemphasis filter 232b.

Variable emphasis filter 560 is designed to have a variable amplituderesponse that closely matches the variable amplitude response of filter136 (shown in FIG. 1) of idealized encoder 100. Variable emphasis filter560 provides a similar variable response by using a variable coefficienttransfer function (i.e., the coefficients of the transfer function H(z)of filter 560 are variable) and by allowing LUT 562 to select the valueof the coefficients during intervals based on the sample period. As willbe described in greater detail below, LUT 562 stores the values of thefilter coefficients used by filter 560, and during each sample period,or during any selected group of sample periods, LUT 562 selects a set offilter coefficients as a function of the output signal generated bylogarithmic generator 558 on line 558 a. In one preferred embodiment,variable emphasis filter 560 is implemented as a first order IIR filterhaving a transfer function H(z) that is described by the formula shownin the following Equation (6).

$\begin{matrix}{{H(z)} = \frac{b_{0} + {b_{1}z^{- 1}}}{1 + {a_{1}z^{- 1}}}} & (6)\end{matrix}$

in which the filter coefficients b₀, b₁, and a₁ are variables that areselected by LUT 562. Methods of selecting the values for the filtercoefficients used by filter 560 as well as by the other filters ofencoder 200 will be discussed below.

In FIG. 6, logarithmic generator 558 and square root device 556 areshown, for convenience, as two separate components. However, thoseskilled in the art will appreciate that these two components may beimplemented using a single device, such as a LUT, or alternatively usingprocessing components that calculate a Tayler series polynomialapproximation of the logarithm of the signal on line 554 a and by thendividing this value by two. Similarly, in alternative implementations,the functions performed by logarithmic generator 558, square root device556, and LUT 562 maybe incorporated into a single device.

As stated above, high pass filters 212, 214 (shown in FIG. 3) are usefulin blocking DC components so as to prevent encoder 200 from exhibiting abehavior known as “ticking”. In the context of a stereophonic encoder,ticking refers to relatively low frequency oscillatory behavior of theencoder caused when there is no signal present at the left and rightchannel audio inputs. The desired behavior of a stereophonic system whenthere is no signal present at the audio inputs is to remain silent;however, an encoder connected through a decoder to loudspeakers andexhibiting ticking causes the loudspeakers to emit an audible sound,referred to as a “tick”, with a somewhat regular period that ispartially dependent on the time constant of the RMS level detector inthe wideband compressor. More particularly, in encoder 200, when onlyvery low level signals are present at the audio inputs, and when thereis a D.C. component, or an offset, present in the signal on line 239,wideband compression unit 280 tends to behave in an unstable fashionthat causes ticking.

Consider the case where only a low level audio signal is present on line239. In such a case, the output of RMS level detector 450 on line 450 abecomes very small, which in turn causes the gain of multiplier 434 tobecome very large. If such a low level audio signal on line 239 isconstant in its amplitude, the wideband compression unit 280 reaches asteady-state condition after some time (determined by the time constanta applied to multiplier 460), because the encoded difference signal isfed back on line 240 to the wideband compression unit 280. Because thefeedback is arranged to be negative, when the audio signal on line 239increases in its amplitude, the signal on line 450 a increases, which inturn causes the gain of multiplier 434 to decrease. When the audiosignal on line 239 decreases in its amplitude, the signal on line 450 adecreases, which in turn causes the gain of multiplier 434 to increase.

However, should there be a significant dc signal present on line 239 inaddition to a low level audio signal, the dc signal is blocked from thefeedback process by the action of wideband bandpass filter 448, whichhas zero response to dc signals. In particular, any dc present in theencoded difference signal at line 240 is blocked by filter 448, and isnot sensed by RMS level detector 450. Any dc signal present on line 239will be amplified by multiplier 434 along with any audio signal presenton line 239, but the amplification factor or gain will be determinedonly by the audio signal amplitude as sensed by RMS level detector 450after filtering by filter 448.

As noted above, whenever the amplitude of the audio signal on line 239varies, the gain of multiplier 434 varies inversely. During suchvariations in gain, any dc present on line 239 will also be subjected tovariable amplification, in effect modulating the dc signal, therebyproducing an ac signal. In this fashion such dc signals may be modulatedso as to create significant audio-band signals which will not berejected by filter 448, and are therefore sensed by detector 450. Whenthe audio signal on line 239 is small compared to the do on line 239,small variations in the audio signal level, which cause changes in thegain of amplifier 434, can cause a large change in the dc level (whichamount to an ac signal) at line 281 through this modulation process. Theac signal produced tends to increase the overall signal which passesthrough filter 448, regardless of whether the audio signal variationthat gave rise to the ac signal was an increase or decrease in signallevel. In particular, should the level of the audio signal on line 239decrease, the negative feedback process normally increases the gain ofmultiplier 434. However, if a sufficient dc signal is present in line239, a decrease in audio signal on line 239 can cause an increase in thesignal sensed by detector 450, forcing the gain of multiplier 434 todecrease. In this fashion, the negative feedback process is reversed,and the feedback becomes positive.

Such positive feedback will only persist so long as the modulated dcsignal at line 281 is sufficiently large compared to any audio signalpresent on line 281, when weighted by the response of all the filtersand signal modifiers between line 281 and the output of filter 448. Oncethe gain of multiplier 434 decreases sufficiently such that themodulated dc signal in line 281 no longer provides a significant inputto detector 450, the feedback reverts to its normal negative sense. Inaccordance with the time constant of detector 450, the system willre-acquire an appropriate gain level based on the level of the audiosignal in line 239. But, if sufficient dc remains in the signal in line239, the cycle will repeat itself once the gain of multiplier 434increases sufficiently. During each such period of positive feedback, asharp change in the dc level of line 281 is produced. This change isaudible, and sounds somewhat similar to the ‘tick’ of a clock. Sincesuch dc changes will occur with some regularity, based on the timeconstant of detector 450, the phenomenon is often referred to as‘ticking’

One method of preventing ticking is to remove any do components presentin the input signal to encoder 200. This is accomplished by high passfilters 212 and 214. Further, high pass filters 212 and 214 help tomaximize the dynamic range of encoder 200 by removing dc componentswhich otherwise may use up valuable dynamic range.

As stated above and as shown in FIG. 3, low pass filter 238 ispreferably implemented as two filters 238 a and 238 b. Splitting filter238 in this fashion provides several advantages. If filter 238 a wereeliminated, and the entire filter 238 were located after clipper 254(i.e., in the location of filter 238 b) then any components above 15 kHzon the audio input signals may cause instability in the widebandcompression unit 280 similar to the above-described ticking behavior.This occurs because any signal components above 15 kHz on line 239 willbe amplified by multiplier 434 (shown in FIG. 5) and because suchcomponents will not be sensed by RMS level detector 450 since suchcomponents are filtered out by the low pass filter following clipper 254(shown in FIG. 3). Since detector 450 increases the gain of multiplier434 when it senses the absence of a signal, the gain of multiplier 434can become relatively large when the signal on line 239 consists oflittle audio signal (under 15 kHz) information, but significant highfrequency (over 15 kHz) information. Multiplier 434 then amplifies thehigh frequency information, which can generate large signals that arelikely to be clipped by components in processing section 230. Thisclipping can produce harmonics which may alias to low frequencies thatwill be sensed by RMS level detector 450 causing the system to tick asdescribed previously. Alternatively, if filter 238 b were eliminated andthe entire filter 238 were located before fixed preemphasis filter 232 a(i.e., in the location of filter 238 a) then high frequency artifactsgenerated by clipper 254 would be included in the encoded differencesignal and could interfere with the pilot tone in the composite signal.Therefore, splitting filter 238 as shown provides an optimal arrangementwhereby filter 238 a prevents ticking in compression unit 280 and filter238 b filters high frequency artifacts that may be generated by clipper254.

Fixed preemphasis filter 232 is also preferably split into two filters232 a, 232 b as shown in FIG. 3. Filter 232 typically requiresrelatively large gain at high frequencies, as is specified in the BTSCstandard, and using only a single section to implement filter 232increases the likelihood of filter 232 causing clipping. It isadvantageous to apply some of the gain of filter 232 on the input sideof wideband compression unit 280 (with filter 232 a) and to apply someof the gain of filter 232 on the output side of wideband compressionunit 280 (with filter 232 b). Since unit 280 normally compresses itsinput signal, distributing the gain of filter 232 around the compressionprovided by unit 280 decreases that the likelihood that the gain offilter 232 will cause an overflow condition.

To minimize size, power consumption, and cost, encoder 200 is preferablyimplemented using a single digital signal processing chip. Encoder 200has been successfully implemented using one of the well known MotorolaDSP 56002 digital signal processing chips (this implementation shall bereferred to hereinafter as the “DSP Embodiment”). The Motorola DSP 56002is a fixed point twenty-four bit chip, however, other types ofprocessing chips, such as floating point chips, or fixed point chipshaving other word lengths, could of course be used. The DSP Embodimentof encoder 200, uses a sampling frequency fs that is equal to threetunes the pilot frequency f_(H) (i.e., f_(s)=47202 Hz). The followingTable 1 lists all of the filter coefficients used in the DSP Embodimentof encoder 200 except those used in variable emphasis filter 560.

TABLE 1 Low Pass Filter (Section #1) 310 Low Pass Filter (Section #2)312 (Equation 4) (Equation 4) b₀ = 0.18783270 b₀ = 0.44892888 b₁ =0.36310206 b₁ = 0.70268024 b₂ = 0.18783270 b₂ = 0.44892888 a₁ =−0.388832539 a₁ = 0.12638618 a₂ = 0.12709286 a₂ = 0.47415181 Low PassFilter (Section #3) 314 Low Pass Filter (Section #4) 316 (Equation 4)(Equation 4) b₀ = 0.70674027 b₀ = 0.85733126 b₁ = 0.87637648 b₁ =0.91505047 b₂ = 0.70674027 b₂ = 0.85733126 a₁ = 0.53702472 a₁ =0.74320197 a₂ = 0.75298490 a₂ = 0.89832289 Low Pass Filter (Section #5)318 Wideband Bandpass Filter 448 (Equation 4) (Equation 4) b0 =0.92737972 b₀ = −0.02854672 b1 = 0.92729649 b₁ = −0.18789051 b2 =0.92737972 b₂ = 0.21643723 a₁ = 0.82951974 a₁ = −1.75073141 a₂ =0.97259237 a₂ = 0.75188028 Fixed Preemphasis Filter 238a FixedPreemphasis Filter 238b (Equation 2) (Equation 2) b₀ = 9.50682180 b₀ =4.357528 b₁ = 9.00385663 b₁ = −3.24843271 a₁ = −0.497064357 a₁ =0.10881833 Spectral Bandpass Filter Spectral Bandpass Filter (Section#3) 542a (Section #2) 542b (Equation 4) (Equation 4) b₀ = 0.646517841 b₀= 0.850281278 b₁ = 0.649137616 b₁ = −0.850247036 b₂ = 0.0 b₂ = 0.0 a₁ =0.557821757 a₁ = −0.602159890 a₂ = 0.0 a₂ = 0.0 Spectral Bandpass FilterStatic Phase Equalization Filter (Section #3) 542c 224 (Equation 4)(Equation 3) b₀ = 0.597678418 a₀ = 0.9029 b₁ = −1.195357770 b₂ =0.597679348 a₁ = −0.776566094 a₂ = 0.352824276 75 μs preemphasis filter222 High Pass Filters 212, 214 (Equation 2) (Equation 1) b₀ = 4.57030583a₁ = −0.999 b₁ = −3.43823487 a₁ = 0.131778883

In the DSP Embodiment of encoder 200 the value of the constant a that isused by averager 454 (shown in FIG. 5) in wideband compression unit 280is set equal to 0.0006093973517, and the value of the constant β that isused by averager 554 (shown in FIG. 6) in spectral compression unit .290is set equal to 0.001825967. Further, the values of Gain C and Gain Dused by amplifiers 540 and 446, respectively, in the spectral andwideband compression units are set equal to 0.5011872 and 0.08984625,respectively, to insure that the DSP Embodiment of encoder 200 performssimilarly to encoder 100.

FIG. 7 shows a flow chart 700 that describes one preferred method forpre-calculating all the sets of filter coefficients used by variableemphasis filter 560 (shown in FIG. 6) in the DSP Embodiment of encoder200. Prior to operation of encoder 200, all the sets of filtercoefficients used by filter 560 are pre-calculated (e.g., by a generalpurpose digital computer) and are loaded into LUT 562. In the DSPEmbodiment of encoder 200, filter 560 has a transfer function H(z) thatis described by Equation (6) so flow chart 700 describes the calculationof the coefficients b₀, b₁, and a₁. As specified in the BTSC standard,the transfer function of S(f,b) of analog filter 136 (shown in FIG. 1)to which filter 560 partially corresponds, is described by the formulashown in the following Equation (7).

$\begin{matrix}{{S\left( {f,b} \right)} = \frac{1 + \frac{\left( \frac{jf}{F} \right)\left( {b + 51} \right)}{\left( {b + 1} \right)}}{1 + \frac{\left( \frac{jf}{F} \right)\left( {1 + {51b}} \right)}{\left( {b + 1} \right)}}} & (7)\end{matrix}$

in which F is equal to 20.1 kHz.

The first step in flow chart 700 in an initialization step 710 duringwhich several variables are initialized. Specifically, the samplingfrequency f_(s) is set equal to 47202 Hz, and the period T is set equalto Vt. The variable W is a digital version of the variable F used inEquation (7) and is set equal to n(20.1 kHz)/f_(s). The variable dBRANGErepresents the desired signal range of the RMS detectors in the spectralcompression unit, and for the DSP Embodiment ORANGE is set equal to72.25 M. The variable dBRF.S relates to the sensitivity of filter 560 tochanges in the energy level of the encoded difference signal. In the DSPEmbodiment of encoder 200, dBRES is set equal to 0.094 dB so that filter560 will use coefficients based on the value of the signal on line 558 aquantized to the nearest 0.094 db. The variable N equals the totalnumber of sets of filter coefficients used in filter 560 and N iscalculated by dividing the sensitivity (dBRES) into the range (dBRANGE)and rounding to the nearest integer. In the DSP Embodiment, N is equalto 768 although those skilled in the art will appreciate that thisnumber can be changed which will vary the sensitivity or the range. Inthe DSP Embodiment, LUT 562 stores 769 sets of coefficients for filter560, and of course if N is increased, a larger LUT will be used to storethe extra sets of filter coefficients. Further, those skilled in the artwill appreciate that logarithmic generator 558 scales the signal on line558 a and thereby reduces the number of filter coefficient sets storedby LUT 562, for a given minimum quantization of the value of the signalon Line 558 a. However, in other embodiments, logarithmic generator 558may be eliminated and LUT 562 may store a correspondingly larger numberof filter coefficient sets. Finally, the variables Scale and Address areset equal to 32 and zero, respectively. The variable Scale, which isonly used in fixed point implementations, is selected so that all thefilter coefficients have a value greater than or equal to negative oneand less than one (where the filter coefficients are represented in twoscomplement).

Following initialization step 710, a coefficient generation step 720 isexecuted. During the first execution of step 720, variables b₀(0),b₁(0), and a₁(0) are calculated which correspond to values of thecoefficients bo, b1, and a1 that are to be stored at address locationzero of LUT 562. Following this execution of step 720, an incrementingstep 730 is executed during which the value of the variable Address isincremented. Following step 730 a comparison step is executed duringwhich the values of the variables Address and N are compared. If Addressis less than or equal to N, then steps 720, 730, and 740 are reexecutediteratively so that values of the coefficients bo, b1, and a1 arecalculated for each of the 769 addresses of LUT 562. When step 740detects that the value of Address is greater than N, then all 769 setsof coefficients have been calculated and execution of flow chart 700proceeds to a concluding step 750.

In coefficient generation step 720, the variable dBFS corresponds to theoutput of logarithmic generator 558. As the value of the variableAddress ranges from zero to 769, the value of dBFS ranges from about−72.25 to zero dB corresponding to the signal range of about 72.25 dBprovided by the DSP Embodiment of encoder 200 (where zero dB correspondsto the full modulation). The variable RMSd corresponds to the output ofthe analog RMS level detector 144 (shown in FIG. 1), and as the variableAddress ranges from zero to 769, the value of RMSd ranges from about −36to 36 dB corresponding to the signal range of 72 dB provided by typicalprior art analog BTSC encoders. The variable RMSb is a linear version ofthe variable RMSd, and RMSb corresponds to the variable b in thetransfer function S(f,b) described in Equation M. The variables K1 andK2 correspond to the (b+51)/(b+1) and the (51b+1)/(0+1) terms,respectively, in Equation (7). The coefficients b₀, b₁, and a₁ arecalculated as shown in step 720 using the variables K1, K2, W, andScale.

FIG. 8A shows a block diagram that illustrates one method of using theDSP Embodiment in an analog system, and in FIG. 8A, all components thatare implemented in the 56002 integrated circuit are indicated at 200 a.The analog system supplies analog left and right channel audio inputsignals (shown in FIG. 8A as “L” and “R”, respectively) and thesesignals are applied to the inputs of sixteen bit analog-to-digitalconverters 810 and 812, respectively. Converters 810, 812 sample theiranalog input signals using a sampling frequency f_(s) that is equal to47,202 Hz (i.e., 3f_(H)) and converters 810, 812 thereby generatesequences of sixteen bit digital samples that are representative of theleft and right channel audio input signals, respectively. The signalsgenerated by converters 810 and 812 are applied to encoder 200 a wherethey are received by modules 292 and 294, respectively. Modules 292, 294are “divide by sixteen” modules (which divide the amplitude of theirinputs by a factor of 16) and therefore generate output signals that areequal to their input signals divided by sixteen. Since division by anypower of two is easily accomplished in a digital system by using a shiftregister, modules 292, 294 are implemented as shift registers that shifttheir inputs by four binary places.

As stated above, the 56002 chip is a fixed point twenty-four bitprocessor, and the samples applied to the chip by converters 810, 812are in twos complement representation. Modules 292, 294 divide thesamples generated by converters 810, 812 by sixteen and thereby placeeach of the samples in the middle of a twenty-four bit word. So in everysample generated by modules 292, 294, the four most significant bits aresign bits and the four least significant bits are zeros, and the sixteenbits in the middle of the word correspond to one sample generated by oneof the converters 810, 812. Padding each twenty-four bit word with signbits at the high end and with zeros at the low end in this fashionpreserves accuracy and allows intermediate signals generated by encoder200 a to exceed sixteen bits without causing an error condition such asan overflow.

In encoder 200 a, each bit of the twenty-four bit word correspondsroughly to 6 dB of signal range, and therefore modules 292, 294correspond to −24 dB (i.e., negative 6 times 4) attenuators. If theanalog input signals applied to converters 810, 812 are considered forreference purposes as zero dB signals, then the signals generated bymodules 292, 294 are attenuated by 24 dB.

Input section 210 receives the twenty-four bit words generated bymodules 292, 294 and generates therefrom the sum signal that is appliedto the sum channel processing section 220. The output signal generatedby sum channel processing section 220 is applied to a “times 16 module”(which may be considered as a 24 dB amplifier) 296. Module 296 therebycompensates for the −24 dB attenuators 292, 294 and brings the output ofsum channel processing section 220 back to 100% modulation (i.e., backto “full scale”). The output signal generated by module 296 is appliedto a sixteen bit digital-to analog converter 814 which in turn generatesan analog conditioned sum signal.

Input section 210 also generates the difference signal that is appliedto the difference channel processing section 230. As stated above, as aresult of modules 292, 294, the difference signal may be considered asbeing attenuated by 24 dB. In the DSP embodiment of encoder 200 a,clipper 254 (shown in FIG. 3) of the difference processing section 230includes an 18 dB amplifier (which is implemented as a multiply byeight). That is, clipper 254 amplifies the signal generated by fixedpreemphasis filter 232 b by 18 dB and then clips this amplified signalso that the output signal generated by clipper 254 will not exceed anumber that is 6 dB down from full modulation. The signal applied fromclipper 254 to low pass filter 238 b therefore has one bit (or 6 dB) of“headroom”, so filter 238 b may generate an output signal that is 6 dBgreater than its input signal without causing saturation. It isdesirable to leave this one bit of headroom because the transientresponse of filter 238 b includes some ringing that may cause it totemporarily generate an instantaneous output signal that is greater thanits instantaneous input signal and the headroom thereby prevents anyringing in filter 238 b from causing a saturation condition. Referringagain to FIG. 8A, the output signal generated by filter 238 b is appliedto a sixteen bit digital-to-analog converter 816 which in turn generatesan output signal that is applied to a 6 dB analog amplifier 820. BothD/A converters 814 and 816 are intended to be complete converters, whichinclude the well-known analog anti-image filters as part of theirfunctionality. Anti-image filters are analog filters applied to theanalog signal following digital to analog conversion which serve toattenuate any images of the desired signal which are mirrored about thesample frequency and multiples thereof. Converters 814 and 816 areassumed to be substantially identical to one another, running at thesame sample rate and containing substantially the same anti-imagefiltering. Such converters are commonly available in commercialembodiments, such as the Crystal Semiconductor CS4328. Amplifier 820amplifies its input signal by 6 dB and thereby brings the encodeddifference signal back up to full scale. While FIG. 8A shows encoder 200a coupled to analog-to-digital converters 810, 812 for receiving analogaudio signals, in digital systems converters 810, 812 may of course beeliminated so that encoder 200 a receives the digital audio signalsdirectly.

FIG. 8B shows a block diagram of one preferred embodiment of a BTSCencoder 200 b constructed according to the invention and configured aspart of an analog system. Encoder 200 b is similar to encoder 200 a,however, in encoder 200 b module 296 amplifies its input signal by 18 dB(by multiplying by 8) rather than by 24 dB as in encoder 200 a. Theoutput signal generated by module 296 is a scaled version of theconditioned sum signal and is shown in FIG. 8B as S. Also, encoder 200 bincludes a module 298 for amplifying the output signal generated bydifference channel processing section 230 by 6 dB (by multiplying bytwo). The output signal generated by module 298 is a scaled version ofthe encoded difference signal and is shown in FIG. 8B as D. Further,encoder 200 b includes a composite modulator 822 for receiving thesignals S and D and for generating therefrom a digital version of thecomposite signal. The digital composite signal generated by modulator822 is applied to a digital-to-analog converter 818 the output of whichis an analog version of the composite signal. D/A converter 818 isintended to be a complete converter which includes the aforementionedanalog anti-image filter as part of its functionality. Such convertersare commonly available in commercial embodiments, such as the Burr-BrownPCM1710. In the preferred embodiments, modules 292, 294, input section210, sum channel processing section 220, difference channel processingsection 230, modules 296, 298, and composite modulator 822 are allimplemented on a single digital signal processing chip.

Since the composite signal is generated as a digital signal in encoder200 b, module 298 is included to bring the output signal generated bydifference channel processing section 230 up to full scale rather thanwaiting until after digital-to-analog conversion and using an analogamplifier such as amplifier 820 as is shown in FIG. 8A. Also, since inthe composite signal the conditioned sum signal is used at 50%modulation, module 296 only amplifies its input signal by 18 dB so thatthe output signal generated by module 296 is at half the amplitude ofthe output signal generated by module 298.

FIG. 9 shows a block diagram of one embodiment of composite modulator822. The latter receives the signals S and D and generates therefrom adigital version of the composite signal. Modulator 822 includes twointerpolators 910, 912, two digital low pass filters 914, 916, a digitalsignal multiplier 918, and two digital signal adders 920, 922. The S andD signals are applied to respective inputs of the interpolators 910 and912. Interpolators 910, 912, which are alternatively referred to as“up-samplers”, interpolate a new sample between every two consecutivesamples applied to their inputs, and thereby generate output signalshaving twice the sampling frequency as the input signals S and D. Theoutput signals generated by interpolators 910 and 912 are applied torespective inputs of low pass filters 914 and 916. The latter removeimages introduced into the S and D signals by interpolators 910, 912.The filtered output signal generated by filter 916 is applied to oneinput of signal multiplier 918 and a digital oscillating signal as afunction of cos [4π(ƒ_(H)/ƒ_(s))n] is applied to the other input ofmultiplier 918. Multiplier 918 thereby generates the amplitudemodulated, double-sideband, suppressed carrier version of the differencesignal that is used in the composite signal. The output signal generatedby multiplier 918 is applied to one input of signal adder 920 and thefiltered output signal generated by filter 914 is applied to the otherinput of signal adder 920. The latter generates an output signal bysumming the two signals present at its inputs and applies this signal tosignal adder 922. A pilot tone signal that oscillates as a function of Acos [2π(ƒ_(H)/ƒ_(s))n] (where ‘A’ is a constant representative of 10% offull scale modulation) is applied to the other input of signal adder 922which generates the digital composite signal by summing the two signalspresent at its inputs.

Composite modulator 822 includes interpolators 910, 912 because thehighest frequency component in the composite signal is slightly lessthan 3f_(H) (as is shown in FIG. 2), and therefore the signals appliedto the inputs of signal multiplier 918 and signal adder 920 should havesample rates at least as large as 6f_(H) to satisfy the Nyquistcriteria. Because the sample rate at the output of composite modulator822 is typically higher than the sample rate of either the S or Dsignals, D/A converter 818 must be capable of operating at such highersample rates. If the input signals S and D applied to compositemodulator 822 have sample rates of 3f_(H) some form of interpolation(such as that provided by interpolators 910, 912) should be provided todouble the sample rate. Of course, if sufficiently high sample rates areused throughout encoder 200 b then interpolators 910, 912 and low passfilters 914, 916 may be eliminated from modulator 822.

FIG. 8C shows a block diagram of yet another embodiment of a BTSCencoder 200 c constructed according to the invention. Encoder 200 c issimilar to encoder 200 b (shown in FIG. 8B) however, in encoder 200 cmodule 298 is eliminated so that the signal generated by the differencechannel processing section 230 is the signal D and is applied directlyto composite modulator 822. Further, in encoder 200 c, module 296amplifies its input signal by 12 dB (by multiplying by 4) rather than by18 dB as is done in encoder 200 b. So in encoder 200 c, the signals Sand D are 6 dB down from the levels of those signals in encoder 200 b.Composite modulator 822 therefore generates from these signals a versionof the composite signal that is attenuated by 6 dB. This attenuatedversion of the composite signal is converted to an analog signal bydigital-to-analog converter 818 and is then brought up to full scale by6 dB analog amplifier 820. As with encoder 200 b, encoder 200 c ispreferably implemented using a single digital signal processing chip.

The differences between encoders 200 b and 200 c represent designtradeoffs. As those skilled in the art will appreciate, when convertinga digital signal to an analog signal with a digital-to-analog converter,insuring that the digital signal is at full scale tends to minimize anyloss of signal-to-noise ratio that might occur as a result of theconversion. Encoder 200 b minimizes the loss of signal-to-noise ratio asa result of the operation of converter 818 by using modules 296, 298 toinsure that the digital version of the composite signal (generated bymodulator 822) that is applied to converter 818 is at full scale.However, although converter 200 b minimizes any loss of signal-to-noiseratio that might occur as a result of converter 818, encoder 200 b alsoincreases the likelihood that clipping might occur in the compositesignal. Since the difference channel processing section 230 uses therelatively large gain provided by fixed preemphasis filter 232 (shown inFIG. 3), it is possible for some clipping to occur in the path of theencoded difference signal. Encoder 200 b uses module 298 to bring the Dsignal up to full scale and this essentially eliminates any headroomfrom the signal path of the D signal and thereby increases the chancethat some clipping will occur. So encoder 200 b minimizes the loss ofany signal-to-noise ratio that occurs as a result of converter 818 atthe cost of increasing the likelihood of clipping in the path of theencoded difference signal. In contrast, encoder 200 c preserves headroomin the path of the encoded difference signal and thereby reduces thelikelihood of clipping at the cost of increasing the loss ofsignal-to-noise ratio that occurs as a result of operation of converter818.

FIG. 8D shows a block diagram of yet another embodiment of a BTSCencoder 200 d constructed according to the invention. Encoder 200 d issimilar to encoder 200 a (shown in FIG. 8A) however, encoder 200 dadditionally includes a portion 822 a of a composite modulator. Portion822 a includes two interpolators 910, 912, two low pass filters 914,916, digital signal multiplier 918 and a digital signal adder 930. The Ssignal generated by module 296 is applied to interpolator 910 which“up-samples” the S signal and applies the up-sampled signal to low passfilter 914. The latter filters this signal and applies the filteredsignal to one input terminal of adder 930. A digital pilot tone havingtwice the normal amplitude (i.e., 2A cos 2π(f_(H)/f_(s))n) is applied tothe other input terminal of adder 930 which generates an output signalby summing the two signals present at its input terminals. The D signalgenerated by difference channel processing section 230 is applied tointerpolator 912 which generates an up-sampled signal that is applied tolow pass filter 916. The latter filters this signal and applies thefiltered signal to one terminal of multiplier 918. A signal oscillatingaccording to cos 4π(f_(H)/f_(s))n is applied to the other terminal ofmultiplier 918 which generates an output signal by multiplying the twosignals present at its input terminals. As with encoders 200 a-c,encoder 200 d is preferably implemented using a single digital signalprocessing chip.

Encoder 200 d is preferably used in conjunction with twodigital-to-analog converters 932, 934, an analog −6 dB attenuator 936,an analog 6 dB amplifier 938, and an analog adder 940. The output signalgenerated by adder 930 is applied to converter 932 which generates ananalog signal that is applied to attenuator 936. The output signalgenerated by multiplier 918 is applied to converter 934 which generatesan analog signal that is applied to amplifier 938. The signals generatedby attenuator 936 and amplifier 938 are applied to input terminals ofsignal adder 940 which sums these signals to generate the analogcomposite signal. D/A converters 932 and 934 are intended to be completeconverters which include the aforementioned analog anti-image filters aspart of their functionality. Converters 932 and 934 are assumed to besubstantially identical to one another, running at the same sample rateand containing substantially the same anti-image filtering. Suchconverters are commonly available in commercial embodiments, such as theBurr Brown PCM1710.

It is also possible to eliminate interpolator 910 and low pass filter914 from FIG. 8D, and run D/A converter 932 at a sample rate equal tothat of the sum channel processing section 220. However, to do so isgenerally not practical because inexpensive, commonly available D/Aconverters are usually available in pairs housed within a singleintegrated circuit. Such paired D/A converters naturally operate at thesame sample rate. While it is possible to reduce DSP complexity byeliminating interpolator 910 and low pass filter 914 from FIG. 8D, doingso would also likely increase the cost and complexity of the overalldesign because a simple stereo D/A converter could no longer be used forboth D/A converters 932 and 934.

Encoder 200 d represents one combination of the features of encoders 200b and 200 c. Encoder 200 d uses module 296 to bring the S signal up tofull scale so as to minimize any loss of signal-to-noise ratio thatmight occur as a result of the operation of converter 932. Encoder 200 dalso preserves 6 dB of headroom in the signal path of the D signal andtherefore reduces the likelihood of any loss of accuracy due toclipping. Although encoder 200 d includes more components than either ofencoders 200 b and 200 c, encoder 200 d both minimizes loss ofsignal-to-noise ratio and the likelihood of clipping.

FIG. 10 shows a block diagram of a preferred embodiment of sum channelprocessing section 220 a and difference channel processing section 230 afor use in encoder 200 (and these sections 220 a, 230 a may of course beused in encoders 200 a-d). Processing sections 220 a, 230 a are similarto the. above-described sections 220, 230, however, section 220 aadditionally includes dynamic phase equalization filter 1010, andsection 230 a additionally includes a dynamic phase equalization filter1012. In the illustrated embodiment, the output signals generated bystatic phase equalization filter 228 and fixed preemphasis filter 232 aare applied to the input terminals of dynamic phase equalization filters1010 and 1012, respectively, and the output signal generated bylogarithmic generator 558 on line 558 a is applied to the controlterminals of Mn 1010, 1012. The output signals generated by filters 1010and 1012 are applied to low pass filter 224 and to wideband compressionunit 280, respectively.

Dynamic phase equalization filters 1010, 1012 are used to compensate forphase errors introduced by variable emphasis filter 560 which is used inspectral compression unit 290. The phase response of variable emphasisfilter 560 is preferably matched as closely as is possible to that ofvariable emphasis filter 136 (shown in FIG. 1). However, due to thevariable, signal dependent, nature of variable emphasis filter 136, itis extremely difficult to design variable emphasis filter 560 so thatits phase response is matched to that of variable emphasis filter 136for all pre-emphasis/de-emphasis characteristics, which in turn varieswith signal level. Therefore in typical embodiments of encoder 200, thephase responses of variable emphasis filter 560 and variable emphasisfilter 136 diverge as a function of the signal level. Dynamic phaseequalization filters 1010, 1012 preferably introduce compensatory phaseerrors into the sum and difference channel processing sections tocompensate for the divergence between variable emphasis filter 560 andvariable emphasis filter 136.

Dynamic phase equalization filters 1010, 1012 therefore perform afunction that is similar to that performed by static phase equalizationfilter 228. However, whereas filter 228 compensates for phase errorsthat are independent of the level of the encoded difference signal,filters 1010, 1012 compensate for phase errors that are dependent onthis signal level. Filters 1010, 1012 are preferably implemented as “allpass” filters having relatively flat magnitude responses and selectedphase responses. Dynamic phase equalization filters are included in boththe sum and difference processing sections because a phase delay may berequired in either the sum or difference channel to compensate for thephase error introduced by variable emphasis filter 560. In preferredembodiments, filters 1010, 1012 are implemented in a similar fashion asvariable emphasis unit 536 and include a filter having a variablecoefficient transfer function and a LUT for selecting the values of thefilter coefficients during any particular interval. The signal generatedby logarithmic generator 558 on line 558 a is preferably applied to thecontrol terminals of filters 1010, 1012 and selects the filtercoefficients used by those filters.

Digital encoder 200 has been discussed in connection with certainparticular embodiments, however, those skilled in the art willappreciate that variations of these embodiments are also embraced withinthe invention. For example, variable emphasis unit 536 (shown in FIG. 6)has been discussed in terms of being implemented using a variableemphasis filter 560 and a LUT 562. However, rather than precomputing allthe possible coefficients for filter 560 and storing them in LUT 562, itmay be preferable for other implementations of variable emphasis unit536 to eliminate LUT 562 and to instead include components forcalculating the filter coefficients in real time. Those skilled in theart will appreciate that such considerations represent a tradeoffbetween memory resources (such as are used by a LUT for storing filtercoefficients) and computing resources (such as are used by componentsfor calculating filter coefficients in real time) and may be resolveddifferently in any particular implementation of encoder 200. Similarconsiderations apply to square root devices 456 and 556, reciprocalgenerator 458, and logarithmic generator 558 (shown in FIGS. 5 and 6)which may alternatively use memory resources (e.g., a LUT for storingall the values) or processing resources (e.g., for calculating a Taylorseries polynomial approximation). In yet other embodiments, any or allof the components in encoder 200 may be implemented using individualhardware components or alternatively as software modules running on ageneral or specific purpose computer.

Another example of variations of encoder 200 that are embraced withinthe invention relates to scaling modules 292, 294 (shown in FIG. 8B).The modules are particularly relevant to fixed point implementations ofencoder 200. In floating point implementations there is no need to padeach sample with zeros and sign bits to prevent overflow and thesemodules can therefore be eliminated from floating point implementations.As a further example, the static phase equalization filter 228 (shown inFIG. 10) has been discussed in terms of compensating for phase errorsintroduced by filter 232 a, however, filter 228 may be alternativelyused to compensate for other phase errors introduced by other componentsin the difference channel processing section 230 a. Still further,filters 228 and 1010 may be implemented as a single filter.

Therefore, since certain changes may be made in the above apparatuswithout departing from the scope of the invention herein involved, it isintended that all matter contained in the above description or shown inthe accompanying drawing shall be interpreted in an illustrative and nota limiting sense.

1. A circuit for encoding digital left and digital right audio signalsaccording to the BTSC standard, comprising: a digital matrix unitconfigured to generate a digital sum channel signal and a digitaldifference channel signal; a sum channel processing unit having afrequency response in the digital domain that is substantially equal tothe corresponding analog frequency response specified by the BTSCstandard; and a difference channel processing unit having a frequencyresponse in the digital domain that is substantially equal to thecorresponding analog frequency response specified by the BTSC standard;wherein the sum channel processing unit is configured to produce aconditioned digital sum channel signal in response to the digital sumchannel signal, and the difference channel processing unit is configuredto produce an encoded digital difference channel signal in response tothe digital difference channel signal.
 2. A circuit for encoding digitalleft and digital right audio signals according to claim 1, wherein thedigital matrix unit, the difference channel processing unit, and the sumchannel processing unit are included on a single integrated circuit. 3.A circuit for encoding digital left and digital right audio signalsaccording to claim 1, wherein the digital matrix unit, the differencechannel processing unit, and the sum channel processing unit areimplemented by a digital signal processor.
 4. A system for generating abroadcast television stereo signal from a left-channel signal and aright-channel signal, comprising: a signal combiner arrangementconfigured so as to generate a summation signal comprising the sum of aright digital signal and a left digital signal, and generate adifference signal comprising the difference between the right digitalsignal and the left digital signal; a sum and difference signalgenerator arrangement configured so as to generate a firstpre-emphasized digital signal as a function of the summation signal, anda second pre-emphasized digital signal as a function of the differencesignal; a signal transformation arrangement configured so as totransform the first pre-emphasized digital signal to a digital BTSCcompliant L+R signal, and transform the second pre-emphasized digitalsignal to a digital BTSC compliant L−R signal, wherein the signaltransformation arrangement is configured and arranged to have afrequency response in the digital domain that is substantially equal tothe analog frequency response specified by the BTSC standard; and acomposite signal generator arrangement configured so as to generate adigital composite signal as a function of the combination of the digitalBTSC compliant L+R signal and a modulated version of the digital BTSCcompliant L−R signal.
 5. The system of claim 4, wherein the sum anddifference signal generator arrangement comprises a fixed and variablepre-emphasis network.
 6. A circuit for encoding digital left and digitalright audio signals according to the BTSC standard, comprising: adigital matrix unit configured to generate a digital sum channel signaland a digital difference channel signal; a sum channel processing unit;and a difference channel processing unit; wherein the sum channelprocessing unit is configured to produce a conditioned digital sumchannel signal in response to the digital sum channel signal, and thedifference channel processing unit is configured to produce an encodeddigital difference channel signal in response to the digital differencechannel signal, and wherein the difference between the conditioneddigital sum channel signal and the encoded digital difference channelsignal, for a given frequency and level, conforms substantially with thedifference specified by the BTSC standard.
 7. A circuit for encodingdigital left and digital right audio signals according to claim 6,wherein the digital matrix unit, the difference channel processing unit,and the sum channel processing unit are included on a single integratedcircuit.
 8. A circuit for encoding digital left and digital right audiosignals according to claim 6, wherein the digital matrix unit, thedifference channel processing unit, and the sum channel processing unitare implemented by a digital signal processor.
 9. A system forgenerating a broadcast television stereo signal from a left-channelsignal and a right-channel signal, comprising: a signal combinerarrangement configured so as to generate a summation signal comprisingthe sum of a right digital signal and a left digital signal, andgenerate a difference signal comprising the difference between the rightdigital signal and the left digital signal; a sum and difference signalgenerator arrangement configured so as to generate a firstpre-emphasized digital signal as a function of the summation signal, anda second pre-emphasized digital signal as a function of the differencesignal; a signal transformation arrangement configured so as totransform the first pre-emphasized digital signal to a digital BTSCcompliant L+R signal, and transform the second pre-emphasized digitalsignal to a digital BTSC compliant L−R signal; and a composite signalgenerator arrangement configured so as to generate a digital compositesignal as a function of the combination of the digital BTSC compliantL+R signal and a modulated version of the digital BTSC compliant L−Rsignal, wherein the difference between the digital BTSC compliant L+Rsignal and the digital BTSC compliant L−R signal, for a given frequencyand level, conforms substantially with the difference specified by theBTSC standard.
 10. The system of claim 9, wherein the sum and differencesignal generator arrangement comprises a fixed and variable pre-emphasisnetwork.